Due to the significant advances in the miniaturization of semiconductor devices including CMOS devices, MOSFET operations are close to reaching their physical limits. As the miniaturization advances, characteristics and circuit properties of a CMOS device are difficult to improve simply by scaling of device dimensions including a simple gate length. Therefore, as a method of improving transistor characteristics other than miniaturization, strained silicon technology is being researched. The strained silicon technology is a technology for improving transistor characteristics by increasing the mobility of carriers by applying strain to channel regions of a CMOS transistor. As typical methods of applying strain to channel regions, there is a method of applying a coat of a stress film after forming a transistor or a method of burying a substance having a lattice constant different from silicon into a source/drain region. These methods are being employed for actual products.
Further, there is also a technology of applying stress to a channel by using a volume expansion of a gate (see, for example, Japanese Laid-Open Patent Publication No. 2004-172389). In Japanese Laid-Open Patent Publication No. 2004-172389, a gate is formed by polysilicon and is made amorphous (non-crystal) by injecting an impurity having a relatively large atomic mass number. After arranging the shape, the gate is heated at a temperature of approximately 1000° C. and re-crystallized. In this re-crystallization, by taking advantage of strong compressive stress remaining inside a gate electrode and applying a tensile stress to a channel region below the gate electrode, carrier mobility of an nMOS transistor is improved.
However, with the technology of Japanese Laid-Open Patent Publication No. 2004-172389, due to the gate electrode being formed by amorphous silicon of a single layer, the compressive stress generated in the gate electrode is easily released upward (exerted upward) from the gate electrode. Accordingly, stress cannot be efficiently applied to the channel region immediately below the gate electrode. In order to prevent this from occurring, a cap film may be provided on the gate electrode. However, the presence of the cap film may cause impurities inside the single layer gate electrode to pass through a gate insulating layer and horizontally spread in a surface region of the substrate. In such a case, the distribution of the impurities may be degraded and lead to degrading of transistor characteristics.